No hardware module is complete without a testbench. To verify your 8-bit design, you should simulate corner cases like: : Ensuring the reset/zero logic works.
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The shift‑add multiplier is the direct hardware translation of the paper‑and‑pencil multiplication method: for each 1 in the multiplier, shift the multiplicand and add to an accumulator. This design teaches the fundamentals of partial products and sequential logic.
Here is a behavioral Verilog implementation of the core algorithm for an unsigned sequential multiplier:
// Module: sequential_multiplier_8bit // Description: Low-area, sequential 8-bit multiplier using shift-and-add algorithm. module sequential_multiplier_8bit ( input wire clk, // Clock signal input wire reset, // Active-high synchronous reset input wire start, // Start signal to initiate multiplication input wire [7:0] a, // Multiplicand input wire [7:0] b, // Multiplier output reg [15:0] product, // 16-bit Product result output reg ready // High when multiplication is complete ); reg [7:0] multiplicand; reg [7:0] multiplier; reg [3:0] bit_count; reg [15:0] temp_product; always @(posedge clk) begin if (reset) begin product <= 16'h0000; ready <= 1'b0; bit_count <= 4'd0; temp_product <= 16'h0000; end else if (start && !ready) begin // Initialization phase multiplicand <= a; multiplier <= b; temp_product <= 16'h0000; bit_count <= 4'd0; ready <= 1'b0; end else if (bit_count < 4'd8) begin // Accumulate and shift phase if (multiplier[0]) begin temp_product <= temp_product + (multiplicand << bit_count); end multiplier <= multiplier >> 1; bit_count <= bit_count + 1'b1; end else if (bit_count == 4'd8) begin // Finalize output product <= temp_product; ready <= 1'b1; bit_count <= bit_count + 1'b1; // Prevent continuous execution end end endmodule Use code with caution. 3. Writing the Testbench for Verification
