-gate_clock : Automatically inserts clock-gating cells to drastically reduce dynamic power consumption. 6. Analyzing Synthesis Reports
Limits on fan-out, transition time, and capacitance. 4. Logic Optimization and Compilation synopsys design compiler tutorial 2021
read_verilog rtl/alu.v rtl/regfile.v rtl/top.v current_design MY_TOP link check_design & Test Optimization | Synopsys
Design Compiler: Timing, Area, Power, & Test Optimization | Synopsys synopsys design compiler tutorial 2021